FIG. 1 depicts a conventional output driver circuit. Given the assumption that the gate voltages on both transistor Q1 and transistor Q2 are at ground potential and that the output node O is low, reflections at a mismatched interface may cause output node O to fall below ground to, say, -1.0 volts. Under these conditions, the gate of transistor Q1 becomes positive with respect to the source. Consequently, the channel of transistor Q1 begins to conduct, and the source region of Q1 begins to generate free electron carriers. In an insulated-gate field effect transistor (hereinafter also FET), such as Q1, electric field intensity is greatest near the silicon-silicon dioxide interface where the drain junction is directly under the gate edge. As the free electron carriers from the source region pass through the high-field region near the drain, they can acquire energy far in excess of that which would be attributable solely to ambient temperature. In such a state, those electrons are considered "hot" carriers, and are capable of causing a number of "hot-carrier" effects. For a field effect transistor, the worst case scenario for hot electron generation is generally regarded to be a condition where gate-to-source voltage (V.sub.GS) is about one-half drain-to-source voltage (V.sub.DS).
In MOS memory circuits, "hot-carrier effects" can disturb circuit operation both by directly altering stored data values, and by permanently altering device performance. Although the vast majority of hot electron carriers are collected by the drain region, some leave the channel and travel to the gate through the gate oxide layer. Some of the electrons inevitably become trapped in the gate oxide layer, thereby shifting the threshold voltage of the device. Other electrons are injected into the substrate, through which they can migrate to the memory array where they are attracted by cells in which a logic value of "1" (i.e., a positive charge) is stored. Through this mechanism, data may become corrupted if the refresh cycle is not shortened to compensate for the charge loss. Electron injection into the substrate can also precipitate a latch-up condition in CMOS circuits.
The very structure required to fabricate bulk CMOS circuitry makes it susceptible to latchup. To have both N-channel and P-channel field effect transistors, it is necessary to have both P-type and N-type background material. Typically, the CMOS fabrication process begins with a silicon wafer of a single conductivity type. Regions of the opposite conductivity type, known as wells or tubs, are created it by diffusing or implanting dopant species, which overwhelm the original dopant. For circuitry constructed on a p-type wafer, P-channel FETs are built in an N-well, while N-channel FETs are built directly in the P-type wafer substrate. Unfortunately, the FETs are not the only structures fabricated. PNPN devices consisting of parasitic bipolar transistors are also created. Under certain operational conditions, these PNPN devices can generate a V.sub.CC (power supply voltage) to ground short that can destroy the circuitry.
Some designers have addressed the electron injection problem in output driver circuits by replacing FET Q1 of FIG. 1 with a pair of FETS, Q3 and Q4. Such a circuit is depicted in FIG. 2. Such an approach is effective in reducing electron injection when the output node O drops below ground potential, as transistors Q3 and Q4 act to divide the voltage drop between V.sub.CC and the output node. However, the area required for both FETs Q3 and Q4 is approximately four times that required for transistor Q1 of FIG. 1. Thus, this solution for reducing electron injection has its costs, which for a typical memory circuit can be significant.
What is needed is a new, space-efficient driver circuit that will reduce electron injection into the substrate.